M2GL05 CORE & I/O CCB

MBSTech Universal IGLOO2 FPGA Common Circuit Block
Revision: Rev00a
Author: Andrew (Andy) Carpenter — MBSTech


1. Overview

The M2GL05 CORE & I/O CCB (Common Circuit Block) is a reusable, highly-reliable digital core designed around the Microchip IGLOO2 M2GL005 flash-based FPGA.

It is intended for use in electrically demanding and safety-critical environments such as:

• High-voltage power conversion systems
• Motor drive and control platforms
• Isolated debug and monitoring systems (Debug POD)
• Industrial and aerospace subsystems
• Deterministic data processing and control applications

The design focuses on deterministic start-up, low power consumption, high noise immunity, and modular I/O flexibility. All FPGA I/O is intentionally left uncommitted to maximise reuse across multiple system architectures.


2. Key Features

• Microchip IGLOO2 M2GL005 FPGA (256-pin VFBGA)
• Flash-based, non-volatile configuration (Instant-On)
• Independent 1.2 V core supply (TPSM828437VCFR)
• Independent 2.5 V bank supply (TPSM828438VCFR)
• 3.3 V primary I/O rail (from system supply)
• Low-jitter programmable clock source (CDC6CE025)
• Filtered PLL analogue supply (BLM15AG601SN1D + MLCC)
• Optional 8 Mb external SRAM (IS66WVQ8M4DBLL-133BLI)
• Fully uncommitted MSIO / DDR / GPIO banks
• JTAG programming & debug interface
• Conservative derating for long-life applications


3. Power Architecture

The CCB requires a regulated 5 V supply (P5V) from the upstream system or isolated power module.

Power distribution is as follows:

P5V
 ├── TPSM828437VCFR → P1V2 (FPGA Core Rail)
 ├── TPSM828438VCFR → P2V5 (FPGA Bank / Auxiliary Rail)
 └── External Regulator → P3V3 (I/O & Peripheral Rail)

The FPGA PLL analogue supply is filtered as:

P3V3 → BLM15AG601SN1D → VDDA
                     → Local MLCC network (100 nF + bulk)

All rails are locally decoupled with carefully placed ceramic capacitors to minimise noise and support transient current demand.

Note: This CCB does not provide galvanic isolation. Isolation is provided by upstream system blocks where required.


4. Supported Interfaces

Interface          Method           Notes
--------------------------------------------------------------
JTAG               Direct           Programming & debug access
MSIO / DDRIO       FPGA-configured  Fully user-assignable
Clock input        CDC6CE025        Low-jitter reference source
External SRAM      Parallel/QSPI    Optional, close-coupled layout

No series termination resistors are used due to extremely short, controlled routing lengths and good signal integrity margins.


5. Supplied Files

This release contains the following files:

m2gl05_fpga_ccb.docx             — Engineering Design Report
m2gl05_fpga_ccb.pdf              — Full Schematic (PDF)
m2gl05_fpga_ccb.SchDoc           — Altium Schematic Source
m2gl05_fpga_ccb.IntLib           — Integrated Library
ReadMe.txt                        — This document


6. Licence

This design is released under the:

CERN Open Hardware Licence v2 – Strongly Reciprocal (CERN-OHL-S)

You may:

• Use
• Study
• Modify
• Build
• Manufacture
• Sell

Provided that:

• Attribution is preserved:
  Andrew (Andy) Carpenter — MBSTech

• All derivative works remain under CERN-OHL-S v2
• Any modifications are disclosed

This work is provided “as-is” with no warranty of any kind.

SPDX-Identifier: CERN-OHL-S-2.0

CERN is referenced solely as the licence steward and does not endorse this design.


7. Author

Andrew (Andy) Carpenter — MBSTech  
M2GL05 CORE & I/O CCB  
Revision: Rev00a — November 2025

